Pixel unit, array substrate and manufacturing method thereof

ABSTRACT

The present disclosure provides a pixel unit, an array substrate and a manufacturing method thereof. The pixel unit comprises slit electrodes and comprises four zones. The slit electrodes in the four zones are electrically connected with each other. The slit incline directions of the slit electrodes of the pixel unit in each of the four zones are the same, and the slit inclined directions of the slit electrodes of the pixel unit in any two adjacent zones of the four zones are different. The pixel unit structure with a plurality of domains and the array substrate comprising the pixel unit structure provided by the present disclosure can eliminate color deviation to the greatest extent, and have excellent light transmittance.

TECHNICAL FIELD

The present disclosure relates to the display field, particularly to apixel unit, an array substrate and a manufacturing method thereof.

BACKGROUND

In the prior art, the pixel unit is generally arranged in an area of aminimum unit enclosed by two adjacent gate lines and two adjacent datalines (wherein the gate lines and the data lines intersect). When theslit incline directions of the slit electrodes (e.g., pixel electrodes)in the pixel unit are same, the light transmittance can be increased,but a color deviation under left and right, upper and lower view anglesmay be caused.

SUMMARY

The technical solution of the present disclosure is proposed withrespect to the above problem in the prior art. The present disclosureprovides a pixel unit structure with a plurality of domains and an arraysubstrate comprising the pixel unit structure, which can eliminate colordeviation to the greatest extent, and have excellent lighttransmittance.

According to an aspect of the present disclosure, a pixel unit isprovided. The pixel unit comprises four zones, and the slit electrodesin the four zones are electrically connected with each other. Slitincline directions of the slit electrodes of the pixel unit in each ofthe four zones are the same, and slit inclined directions of the slitelectrodes of the pixel unit in any two adjacent zones of the four zonesare different.

In one embodiment, the pixel unit is located at a cross position of agate line and a data line, and the four zones of the pixel unit aredelimited by a corresponding gate line and data line.

In one embodiment, the slit incline directions of the slit electrodes ofthe pixel unit in the four zones are in mirror symmetry with respect tothe gate and/or the data line.

In one embodiment, an acute angle between the slit incline direction ofthe slit electrode of the pixel unit and the gate line is in a range of3°-20°.

In one embodiment, an acute angle between the slit incline direction ofthe slit electrode of the pixel unit and the data line is in a range of3°-20°.

In one embodiment, an area enclosed by two adjacent gate lines and twoadjacent data lines is a minimum unit, the four zones of the pixel unitare included in four adjacent minimum units respectively, and eachminimum unit comprises four zones which belong to four adjacent pixelunits respectively.

In one embodiment, slit electrodes in four zones included in a sameminimum unit are electrically isolated from each other, and the slitelectrodes in four zones included in a same minimum unit have a sameslit incline direction.

In one embodiment, opening areas occupied by the four zones are equal.

In one embodiment, the slit electrode is a pixel electrode.

In one embodiment, the pixel unit further comprises a common electrodeand a thin film transistor located at a cross point of a gate line and adata line. Specifically, a source of the thin film transistor iselectrically connected with the data line, and a drain of the thin filmtransistor is electrically connected with the slit electrode through avia hole.

In one embodiment, the slit electrode is a common electrode.

The pixel unit according to the present disclosure is arranged at across position of the gate line and the data line, and comprises fourzones that are delimited by the gate line and the data line andelectrically connected with each other. Since the slit inclinedirections of the slit electrodes of the pixel unit according to thepresent disclosure in any two adjacent zones are different, the pixelunit according to the present disclosure comprises a plurality ofdomains in both the up-down direction and the left-right direction.Hence, the pixel unit according to the present disclosure not onlyimproves the color deviation in the up-down direction but also improvesthe color deviation in the left-right direction. Therefore, the problemof color deviation can be eliminated to the greatest extent.

In addition, since the pixel unit according to the present disclosure isarranged at a cross position of the gate line and the data line, theminimum unit enclosed by two adjacent gate lines and two adjacent datalines can comprise four zones which belong to four adjacent pixel unitsrespectively. The slit electrodes in the four zones included in the sameminimum unit are arranged to have the same slit incline direction.Hence, the orientations of the liquid crystals in the same minimum unitare the same, thereby providing excellent light transmittance.

According to another aspect of the present disclosure, an arraysubstrate is provided. The array substrate comprises a plurality of gatelines and a plurality of data lines in cross arrangement, as well as aplurality of pixel units arranged at cross positions of the gate linesand the data lines. Each pixel unit comprises slit electrodes, and eachpixel unit comprises four zones delimited by the gate line and the dataline. The slit electrodes in the four zones are electrically connectedwith each other. Slit incline directions of the slit electrodes of eachpixel unit in each of the four zones are the same, and slit inclinedirections of the slit electrodes of each pixel unit in any two adjacentzones of the four zones are different.

In one embodiment, an area enclosed by two adjacent gate lines and twoadjacent data lines is a minimum unit, the four zones of the pixel unitare included in four adjacent minimum units respectively, and eachminimum unit comprises four zones which belong to four adjacent pixelunits respectively.

In one embodiment, slit electrodes in four zones included in a sameminimum unit are electrically isolated from each other, and the slitelectrodes in four zones included in a same minimum unit have a sameslit incline direction.

In one embodiment, opening areas occupied by the four zones are equal.

In one embodiment, the slit electrode is a pixel electrode.

The array substrate according to the present disclosure comprises aplurality of gate lines and a plurality of data lines in crossarrangement, as well as a plurality of pixel units arranged at crosspositions of the gate lines and the data lines. Since each pixel unit ofthe array substrate comprises four zones that are delimited by the gateline and the data line and electrically connected with each other, thepixel unit comprises two domains in the up-down direction, and comprisestwo domains in the left-right direction. Hence, the array substrate onthe whole not only improves the color deviation in the up-downdirection, but also improves the color deviation in the left-rightdirection. Therefore, the problem of color deviation is eliminated tothe greatest extent.

The slit electrodes in the four zones included in each of the minimumunits of the array substrate are arranged to have a same slit inclinedirection, such that the orientations of the liquid crystals in the sameminimum unit are the same, thereby enabling the array substrate toprovide excellent light transmittance on the whole.

According to another aspect of the present disclosure, a method ofmanufacturing an array substrate is provided. The method ofmanufacturing an array substrate comprises steps of: forming a pluralityof gate lines and a plurality of data lines in cross arrangement; andarranging a plurality of pixel units at cross positions of the gatelines and the data lines. Each pixel unit comprises slit electrodes, andeach pixel unit comprises four zones delimited by the gate line and thedata line. The slit electrodes in the four zones are electricallyconnected with each other. Slit incline directions of the slitelectrodes of each pixel unit in each of the four zones are the same,and slit inclined directions of the slit electrodes of each pixel unitin any two adjacent zones of the four zones are different.

In one embodiment, an area enclosed by two adjacent gate lines and twoadjacent data lines is a minimum unit, the four zones of the pixel unitare included in four adjacent minimum units respectively, and eachminimum unit comprises four zones which belong to four adjacent pixelunits respectively.

In one embodiment, slit electrodes in four zones included in a sameminimum unit are electrically isolated from each other, and the slitelectrodes in four zones included in a same minimum unit have a sameslit incline direction.

In one embodiment, opening areas occupied by the four zones are equal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other characteristics and advantages of the presentdisclosure will be understood more clearly through the followingdetailed description with reference to the drawings, wherein:

FIG. 1 is a schematic structural view of a pixel unit according to anembodiment of the present disclosure;

FIG. 2 is a schematic structural view of an array substrate according toan embodiment of the present disclosure; and

FIG. 3 schematically shows a flow chart of a method of manufacturing anarray substrate according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the concept of the presentdisclosure will be described in detail with reference to the drawings.

However, the concept of the present disclosure can be illustrated inmany different forms, and should not be understood as being limited tothe particular embodiments expounded in this text. In addition, theseembodiments are provided in order to enable this disclosure to bethorough and complete, and to communicate the scope of the concept ofthe present disclosure to the skilled person in the art completely.

For the sake of clarity, shapes and sizes of the elements can be shownexaggeratedly in the drawings. Moreover, the same reference sign will beused for indicating the same or similar elements throughout.

For the convenience of description, the spatial relative terms such as“under”, “above”, “at the left side of”, “at the right side of” can beused in this text, so as to describe the relationship between oneelement or feature and another (the other) element(s) or feature(s) asshown in the drawings. It should be understood that the spatial relativeterms are aimed at covering different orientations of the devices in useor in operation in addition to the orientations as shown in thedrawings. For example, if the devices in the drawings are put upsidedown, the element that is described as “under other elements orfeatures” will be orientated to be “above other elements or features”.In this way, the exemplary term “under” can cover two orientations:“under” and “above”. Devices can be oriented in other ways (rotated by90 degrees or located at other orientations), and the spatial relativeterms used in this text will make corresponding explanations.

FIG. 1 is a schematic structural view of a pixel unit according to anembodiment of the present disclosure.

As shown in FIG. 1, the pixel unit 10 (a part enclosed by a dotted linein FIG. 1) is located at a cross position of a gate line 20 and a dataline 30. The pixel unit 10 comprises four zones a1, b1, c1 and d1delimited by the gate line 20 and the data line 30. The slit electrodesin the four zones a1, b1, c1 and d1 are electrically connected with eachother. The slit incline directions of the slit electrodes of the pixelunit 10 in any two adjacent zones are different. For example, as shownin FIG. 1, the zone a1 and the zone b1 are two adjacent zones. The slitincline direction of the slit electrode of the pixel unit 10 in the zonea1 differs from the slit incline direction of the slit electrode in thezone b1. In a similar way, the zone a1 and the zone c1 are two adjacentzones. The lit incline direction of the slit electrode of the pixel unit10 in the zone a1 differs from the slit incline direction of the slitelectrode in the zone c1.

The pixel unit 10 is arranged at a cross position of the gate line 20and the data line 30, and comprises four zones a1, b1, c1 and d1 thatare delimited by the gate line 20 and the data line 30 and electricallyconnected with each other. Since the slit incline directions of the slitelectrodes of the pixel unit 10 in any two adjacent zones are different,the pixel unit 10 comprises a plurality of domains in both the up-downdirection and the left-right direction. That is to say, the four zonesa1, b1, c1 and d1 of the pixel unit 10 are formed into four domains. Thepixel unit 10 comprises two domains in the up-down direction and twodomains in the left-right direction. Hence, the pixel unit 10 not onlyimproves the color deviation in the up-down direction but also improvesthe color deviation in the left-right direction. Therefore, the problemof color deviation is eliminated to the greatest extent.

As shown in FIG. 1, the acute angles between the slit incline directionsof the slit electrodes of the pixel unit 10 in the four zones a1, b1, c1and d1 and the gate line 20 are α1, α2, α3 and α4 respectively. The slitincline directions of the slit electrodes of the pixel unit 10 in thefour zones can be in mirror symmetry with respect to the gate line 20,i.e., α1=α3 and α2=α4. In addition, the slit incline directions of theslit electrodes of the pixel unit in the four zones can be in mirrorsymmetry with respect to the data line 30, i.e., α1=α2 and α3=α4.Moreover, the slit incline directions of the slit electrodes of thepixel unit 10 in the four zones can be in mirror symmetric with respectto both the gate line 20 and the data line 30, i.e., α1=α2=α3=α4.

The slit incline directions of the slit electrodes of the pixel unit 10in the four zones a1, b1, c1 and d1 are in mirror symmetry with respectto the gate line 20 and/or the data line 30, such that the liquidcrystal molecules in the pixel unit 10 have uniform stress.

According to an embodiment of the present disclosure, the acute anglesα1, α2, α3 and α4 between the slit incline directions of the slitelectrode of the pixel unit 10 in the four zones a1, b1, c1 and d1 andthe gate line 20 can be in a range of 3-20 degrees. Alternatively, theacute angles between the slit incline directions of the slit electrodeof the pixel unit 10 in the four zones a1, b1, c1 and d1 and the dataline 30 can be in a range of 3-20 degrees.

As shown in FIG. 1, the four zones a1, b1, c1 and d1 of the pixel unitare included in four adjacent minimum units A, B, C and D respectively.Each minimum unit comprises four zones which belong to four adjacentpixel units respectively. Specifically, the zone a1 of the pixel unit 10is included in the minimum unit A, while the minimum unit A furtherincludes three zones a2, a3 and a4 which belong to the other three pixelunits respectively. The zone b1 of the pixel unit 10 is included in theminimum unit B, while the minimum unit B further includes three zonesb2, b3 and b4 which belong to the other three pixel unit respectively.The zone c1 of the pixel unit 10 is included in the minimum unit C,while the minimum unit C further includes three zones c2, c3 and c4which belong to the other three pixel units respectively. The zone d1 ofthe pixel unit 10 is included in the minimum unit D1, while the minimumunit D further includes three zones d2, d3 and d4 which belong to theother three pixel units respectively.

As shown in FIG. 1, the slit electrodes in the four zones included inthe same minimum unit are electrically isolated from each other, and theslit electrodes in the four zones included in the same minimum unit havethe same slit incline direction. Specifically, for example, the slitelectrodes in the four zones a1, a2, a3 and a4 included in the minimumunit A are electrically isolated from each other, because the four zonesa1, a2, a3 and a4 belong to four adjacent pixel units respectively. Inaddition, the slit electrodes in the four zones a1, a2, a3 and a4 havethe same slit incline direction, thereby enabling the slit electrodes inthe minimum unit A to have the same slit incline direction.

The slit electrodes in the four zones included in the same minimum unitare arranged to have the same slit incline direction, such that theorientations of the liquid crystals in the same minimum unit are thesame, thereby providing excellent light transmittance.

The opening areas occupied by the four zones a1, b1, c1 and d1 of thepixel unit 10 can be equal. In addition, the opening areas of the fourzones included in each minimum unit can also be equal. For example, theopening areas of the four zones a1, a2, a3 and a4 included in theminimum unit A are equal.

With respect to the advanced super dimension switch (ADS) display mode,the slit electrode can be a pixel electrode. The pixel unit 10 furthercomprises a common electrode and a thin film transistor located at across point of the gate line 20 and the data line 30. The source of thethin film transistor is electrically connected with the data line 30,and the drain of the thin film transistor is electrically connected withthe slit electrode through a via hole.

Alternatively, the slit electrode can also be a common electrode. It isdirected at the HADS display mode when the slit electrode is a commonelectrode. Because the common electrode is manufactured in one layer andis connected to the same common electrode signal, connection between thezones is not required. By dividing the plate pixel electrode into zonesin the preceding way, the problem of color deviation is eliminated tothe greatest extent.

An insulating layer is arranged between the pixel electrode and thecorresponding common electrode, and the pixel electrode is arrangedabove or under the corresponding common electrode.

FIG. 2 is a schematic structural view of an array substrate according toan embodiment of the present disclosure.

As shown in FIG. 2, the array substrate 100 comprises a plurality ofgate lines 20 and a plurality of data lines 30 in cross arrangement, aswell as a plurality of pixel units 10 arranged at cross positions of thegate lines 20 and the data lines 30. Each pixel unit 10 comprises fourzones a1, b1, c1 and d1 delimited by the gate line 20 and the data line30. The slit electrodes in the four zones a1, b1, c1 and d1 areelectrically connected with each other. Slit incline directions of theslit electrodes of each pixel unit 10 in any two adjacent zones of thefour zones are different.

According to an embodiment of the present disclosure, an area enclosedby two adjacent gate lines 20 and two adjacent data lines 30 on thearray substrate 100 is a minimum unit. The four zones a1, b1, c1 and d1of each pixel unit 10 of the array substrate 100 can be included in fouradjacent minimum units A, B, C and D1 respectively. Each minimum unitcan comprise four zones which belong to four adjacent pixel unitsrespectively.

According to an embodiment of the present disclosure, the slitelectrodes in four zones included in the same minimum unit areelectrically isolated from each other, and the slit electrodes in fourzones included in the same minimum unit have the same slit inclinedirection.

According to an embodiment of the present disclosure, the opening areasoccupied by the four zones a1, b1, c1 and d1 of the pixel unit 10 areequal. Therefore, the opening areas occupied by all zones formed on thearray substrate 100 are equal.

As shown in FIG. 2, the slit electrode according to the presentdisclosure can have a slit in an open form or in a closed form.

The array substrate 100 comprises a plurality of gate lines 20 and aplurality of data lines 30 in cross arrangement, as well as a pluralityof pixel units 10 arranged at cross positions of the gate lines 20 andthe data lines 30. Since each pixel unit 10 of the array substrate 100comprises four zones a1, b1, c1 and d1 that are delimited by the gateline 20 and the data line 30 and electrically connected with each other,the pixel unit 10 comprises two domains in the up-down direction and twodomains in the left-right direction. Hence, the array substrate 100 onthe whole not only improves the color deviation in the up-down directionbut also improves the color deviation in the left-right direction.Therefore, the problem of color deviation is eliminated to the greatestextent.

The slit electrodes in the four zones included in each of the minimumunits of the array substrate 100 are arranged to have the same slitincline direction, such that the orientations of the liquid crystals inthe same minimum unit are the same, thereby enabling the array substrate100 to provide excellent light transmittance on the whole.

FIG. 3 schematically shows a flow chart of a method of manufacturing anarray substrate according to an embodiment of the present disclosure.

As shown in FIG. 3, the method of manufacturing an array substrateaccording to the present disclosure comprises steps of: S1, forming aplurality of gate lines and a plurality of data lines in crossarrangement; and S2, arranging a plurality of pixel units at crosspositions of the gate lines and the data lines. Further, each pixel unitcomprises slit electrodes, and each pixel unit comprises four zonesdelimited by the gate line and the data line, the slit electrodes in thefour zones being electrically connected with each other. Besides, slitincline directions of the slit electrodes of each pixel unit in any twoadjacent zones are different.

According to an embodiment of the present disclosure, an area enclosedby two adjacent gate lines and two adjacent data lines formed on thearray substrate is a minimum unit. The sour zones of the pixel unit canbe included in four adjacent minimum units respectively, and eachminimum unit can comprise four zones which belong to four adjacent pixelunits respectively. In addition, the slit electrodes in the four zonesincluded in the same minimum unit can be electrically isolated from eachother, and the slit electrodes in the four zones included in the sameminimum unit can have the same slit incline direction. The opening areasoccupied by the four zones of the pixel unit can be equal.

By the method of manufacturing an array substrate according to thepresent disclosure, the pixel units are arranged at cross positions ofthe gate lines and the data lines, such that each pixel unit comprisesfour zones delimited by the gate line and the data line. Since eachpixel unit comprises four zones that are divided by the gate line andthe data line and electrically connected with each other, the pixel unitcomprises two domains in the up-down direction and two domains in theleft-right direction. Hence, it not only improves the color deviation inthe up-down direction, but also improves the color deviation in theleft-right direction. Therefore, the problem of color deviation iseliminated to the greatest extent.

The slit electrodes in the four zones included in the same minimum unitare arranged to have the same slit incline direction, such that theorientations of the liquid crystals in the same minimum unit are thesame, thereby providing excellent light transmittance.

Although the embodiments according to the present disclosure have beenillustrated and explained, the ordinary skilled person in the art shouldunderstand that various modifications can be made to these exemplaryembodiments in forms and details without departing from the spirit andthe scope of the concept of the present disclosure defined by the claimsattached.

1. A pixel unit, comprising slit electrodes and four zones, the slitelectrodes in the four zones being electrically connected with eachother, wherein slit incline directions of the slit electrodes of thepixel unit in each of the four zones are the same, and slit inclinedirections of the slit electrodes of the pixel unit in any two adjacentzones of the four zones are different.
 2. The pixel unit according toclaim 1, wherein the pixel unit is located at a cross position of a gateline and a data line, and the four zones of the pixel unit are delimitedby a corresponding gate line and data line.
 3. The pixel unit accordingto claim 2, wherein slit incline directions of the slit electrodes ofthe pixel unit in the four zones are in mirror symmetry with respect tothe gate and/or the data line.
 4. The pixel unit according to claim 2,wherein an acute angle between the slit incline direction of the slitelectrode of the pixel unit and the gate line is in a range of 3°-20°.5. The pixel unit according to claim 2, wherein an acute angle betweenthe slit incline direction of the slit electrode of the pixel unit andthe data line is in a range of 3°-20°.
 6. The pixel unit according toclaim 1, wherein: an area enclosed by two adjacent gate lines and twoadjacent data lines is a minimum unit, the four zones of the pixel unitare included in four adjacent minimum units respectively, and eachminimum unit comprises four zones which belong to four adjacent pixelunits respectively.
 7. The pixel unit according to claim 6, wherein:slit electrodes in four zones included in a same minimum unit areelectrically isolated from each other, and the slit electrodes in fourzones included in a same minimum unit have a same slit inclinedirection.
 8. The pixel unit according to claim 1, wherein opening areasoccupied by the four zones are equal.
 9. The pixel unit according toclaim 1, wherein the slit electrode is a pixel electrode.
 10. The pixelunit according to claim 9, wherein: the pixel unit further comprises acommon electrode and a thin film transistor located at a cross point ofa gate line and a data line, wherein a source of the thin filmtransistor is electrically connected with the data line, and a drain ofthe thin film transistor is electrically connected with the slitelectrode through a via hole.
 11. The pixel unit according to claim 1,wherein the slit electrode is a common electrode.
 12. An arraysubstrate, comprising: a plurality of gate lines and a plurality of datalines in cross arrangement, and a plurality of pixel units arranged atcross positions of the gate lines and the data lines, wherein each pixelunit comprises slit electrodes, and each pixel unit comprises four zonesdelimited by the gate line and the data line, the slit electrodes in thefour zones being electrically connected with each other, and slitincline directions of the slit electrodes of each pixel unit in each ofthe four zones are the same, and slit incline directions of the slitelectrodes of each pixel unit in any two adjacent zones of the fourzones are different.
 13. The array substrate according to claim 12,wherein an area enclosed by two adjacent gate lines and two adjacentdata lines is a minimum unit, the four zones of the pixel unit areincluded in four adjacent minimum units respectively, and each minimumunit comprises four zones which belong to four adjacent pixel unitsrespectively.
 14. The array substrate according to claim 13, whereinslit electrodes in four zones included in a same minimum unit areelectrically isolated from each other, and the slit electrodes in fourzones included in a same minimum unit have a same slit inclinedirection.
 15. The array substrate according to claim 12, whereinopening areas occupied by the four zones are equal.
 16. The arraysubstrate according to claim 12, wherein the slit electrode is a pixelelectrode.
 17. A method of manufacturing an array substrate, comprisingsteps of: forming a plurality of gate lines and a plurality of datalines in cross arrangement; and arranging a plurality of pixel units atcross positions of the gate lines and the data lines, wherein each pixelunit comprises slit electrodes, and each pixel unit comprises four zonesdelimited by the gate line and the data line, the slit electrodes in thefour zones being electrically connected with each other, wherein slitincline directions of the slit electrodes of each pixel unit in each ofthe four zones are the same, and slit inclined directions of the slitelectrodes of each pixel unit in any two adjacent zones of the fourzones are different.
 18. The method according to claim 17, wherein anarea enclosed by two adjacent gate lines and two adjacent data lines isa minimum unit, the four zones of the pixel unit are included in fouradjacent minimum units respectively, and each minimum unit comprisesfour zones which belong to four adjacent pixel units respectively. 19.The method according to claim 18, wherein slit electrodes in four zonesincluded in a same minimum unit are electrically isolated from eachother, and the slit electrodes in four zones included in a same minimumunit have a same slit incline direction.
 20. The method according toclaim 17, wherein opening areas occupied by the four zones are equal.